Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
In a Direct Digital Synthesizer (“DDS”) or a Numerically Controlled Oscillator (“NCO”), a lookup table (“LUT”) may be implemented for performing a phase-to-sinusoid conversion. Conventionally, to reduce the memory footprint of such a LUT, quadrant symmetry is used for storing only a quarter of a full cycle of sinusoid values for purposes of phase-to-sinusoid conversion. The other three quadrants of such a full cycle may be derived by complementing an address input to the LUT or complementing sinusoid values obtained from the lookup table, or a combination thereof. Thus, for example, the mathematical properties of a sine wave may be used, namely sin(180+x)=−sin(x) and sin(180−x)=sin(x), to obtain the other three quarter waves. For obtaining cosine values from a lookup table of sine values, the equation cos(x)=sin(90−x) may be used.
Because only one quadrant of sinusoid values or samples is stored in a LUT, conventionally output from such a LUT was complemented using a 2's complement. An example of a 2's complement output from a LUT may be found in U.S. Pat. No. 6,333,649. It should be appreciated that a sinusoid's amplitude resolution is dependent upon the width of the LUT, whereas the depth of the LUT affects the phase angle resolution of the sinusoid. However, sinusoid values in the LUT are conventionally rounded to accommodate a target amplitude resolution while limiting the bit width.
As rounded sinusoid values in a LUT are conventionally stored as positive numbers, there is no need to store a sign bit. Thus, such sinusoid values stored in a LUT conventionally are unsigned. However, after a sinusoid value is output from a LUT, a logic 0 or 1 may be pre-appended to expressly indicate that the value is either positive or negative, respectively, for using a 2's complement notation. Notably, an unsigned value is conventionally signed prior to any 2's complementing operation on such a value. To negate such a number in such a two's complement representation, all bits of the number are inverted and then a logic 1 is added to the LSB of such an inverted number. This addition of a logic 1 conventionally involves a true arithmetic add rather than simply a logic function applied to each bit independently. In short, this means that a carry chain is implemented for a 2's complement on an output from such a LUT. A carry chain may be speed-limiting with respect to digital signal processing. Thus, a carry chain may be a limit on an upper speed at which a digital signal processing circuit may be operated. Even where ripple carry logic is supported, a carry chain may be a limiting factor in digital signal processing speed. Notably, there are other forms of arithmetic addition that may be implemented, including carry lookahead, and carry-skip, carry-save, among others.
Accordingly, it would be both desirable and useful to provide phase-to-sinusoid conversion without having to use a carry chain as associated with a 2's complement, while having a LUT that stores only a portion for a cycle of a sinusoid.